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Computer architecture

Code: 93020
ECTS: 5.0
Lecturers in charge: izv. prof. dr. sc. Tomislav Hrkać
Lecturers: dr. sc. Sebastijan Horvat - Exercises
English level:


All teaching activities will be held in Croatian. However, foreign students in mixed groups will have the opportunity to attend additional office hours with the lecturer and teaching assistants in English to help master the course materials. Additionally, the lecturer will refer foreign students to the corresponding literature in English, as well as give them the possibility of taking the associated exams in English.

1. komponenta

Lecture typeTotal
Lectures 30
Exercises 30
* Load is given in academic hour (1 academic hour = 45 minutes)
COURSE AIMS AND OBJECTIVES: Getting introduced to computer architecture and organization. Getting introduced to assembly programming.

Definition of the Computer Architecture. Computer Architecture Classification. Turing Machine. Von Neumann Computer Model. Simplified Models of CISC and RISC Processors. ISA Architecture. Control Unit: Hardware and Microprogramming Implementation. Arithmetic-Logic Unit. Data Path. Memory Unit. Hierarchical Organization of Memory System. Cache Memory. Virtual memory. Input/Output Subsystem. Programmed I/O. Interrupt. DMA. Exceptions. Speed-up techniques. Pipelining. Fine- and Coarse-Parallelism. Features of CISC and RISC. Examples of Advanced RISC and CISC Processors.
Exercises are organized as oral lectures as well as laboratory training. The students have to become familiar with assembly programming techniques by using simulators for 16- and 32-bit processors/computers.
1. semester
Mandatory course - Regular study - Mathematics and Computer Science Education
Consultations schedule:


Link to the course web page: https://web.math.pmf.unizg.hr/nastava/gr/